The continued increase in consumers using more data drives a wider adoption of high speed digital signals in electronic products, which increases the complexity of your design, including how to test and debug your product. Making the right decisions early in the process will enable you to avoid prototype re-spins and bring your product to market before the competition.
Keysight's Signal Integrity Hotspots Seminar addresses the challenges facing High Speed Digital designers and developers at component, circuit and system levels.
June 12, 2018 | Trafo, Brown Boveri Pl. 1, 5400 Baden
Please note – Our experts will have Keysight equipment with us, so if you have any other questions regarding other challenges you may have, do not hesitate to ask in a break, and one of the team will be happy to give you a demo and answer any queries.
To characterize high-speed serial buses, jitter measurements are key to determine the quality of the signal being transmitted and provide a quick view of the bit error ratio (BER) that the links support. The measurement of jitter is a sophisticated process taking into account receiver clock recovery, knowledge of phase locked loops (PLLs), jitter decomposition techniques, effects of crosstalk and waveform statistics in order to produce a fairly accurate jitter decomposition model for the real-world designs. This paper will review the details and considerations for making advanced jitter measurements to increase your confidence level in your jitter separation results.
Crosstalk is a huge challenge in today's high-speed serial design because it can corrupt the data transmission, closes the eye-opening as well as adding jitter into your design. Crosstalk can come from various aggressor sources such as adjacent high-speed bus, power supply, phase lock loop and reference clock. Debugging crosstalk issues can be really challenging starting with identifying the aggressors and quantifying how much crosstalk each aggressor is contributing to your signal. In this paper, you will learn how to debug crosstalk issues with a real-time oscilloscope.
When you need to make signal integrity measurements using TDR/TDT, channel quality issues such as reflections, insertion loss and crosstalk can degrade signal integrity.
In this paper, you will learn tips and techniques for using TDR/TDT to accurately characterize channels and identify potential signal integrity issues, including advanced techniques that simplify working with probes and fixtures.
Generally, the signal under test cannot be immediately accessed by your oscilloscope. Instead, the signal must pass through additional components such as connectors, cables, fixtures or probes before it can be measured. Therefore, you end up measuring the signal together with the effects from these additional components. This can inadvertently cause the signal performance to worsen, reducing design margins due to your measurement setup.
De-embedding is a method that is widely used to remove the effects of added components in the signal path, returning the margins to your signal. Although it sounds straightforward, there are limitations and pitfalls to de-embedding that should be avoided. In this paper you will learn more about the practical approach to de-embed the effects of your measurement setup.
It has become much more important to get higher frequency s-parameters for PCB accurately due to ever increasing data rates. ADS 2017 features a host of new technologies designed to improve accuracy of PCB simulations for both signal and power integrity analysis.
This paper covers a signal integrity pre-layout design flow to optimize high speed datalinks in order to maximize the eye opening as well as a post layout verification flow including two electromagnetic (EM) software solutions for model extraction. In the area of power integrity, the tool can analyze the DC IR drop of the power delivery network, the AC impedance and resonances and helps you to optimize your decoupling capacitors. Finally, thermal and electro-thermal analysis is possible on the whole PCB.
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